The present inventive concept relates to static random access memory (SRAM) devices. More particularly, the inventive concept relates to SRAM devices including a write assist circuit and methods of operating same.
Contemporary data processing and consumer electronic devices increasing demand semiconductor memory devices and memory systems capable of operating a high speed. Memory devices and memory systems perform different operations (e.g., read operations, write operations and erase operations) to store data, retrieve stored data, and maintain or manage stored data. Each of these operations requires a certain amount of execution time or “cycle time” to be performed within the memory device or memory system. However, the write operation cycle time (i.e., a period of time required to perform a write operation) that most directly affects or determines the maximum speed at which a memory device or memory system may operate.
Despite the limiting nature of the write operation cycle time, it is critical that input data being written to constituent memory cells (or bit cells) be presented to the memory cells under conditions that ensure proper execution of write operation. For example, the input data must be stably provided during an appropriate timing window and must be presented at discernible voltage levels. As a result, certain contemporary memory devices use a so-called “write assist” techniques to better facilitate the execution of write operations. The write assist functionality is typically provided by a write assist circuit associated with one or more memory cells in an array of memory cells.
Unfortunately, while the use of a write assist circuit better facilitates the accuracy of data outcomes during write operations, it does so at the cost of speed. Plainly stated, the conventional incorporation of write assist circuitry within a memory device tends to further limit the maximum speed at which the memory device may be effectively operated.